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Jean-Luc BECHENNEC

CHERCHEUR

Chargé de Recherche CNRS

: Jean-Luc.Bechennecatls2n.fr

Adresse :

Centrale Nantes ( CN )
Petit Port
1, rue de la Noë
BP 92101
44321 NANTES Cedex 3

Batiment S, étage 5, bureau 509

Publications référencées sur HAL

Revues internationales avec comité de lecture (ART_INT)

[1] A. Bernabeu, M. Briday, S. Faucou, J. Béchennec, O. Roux. Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems. In Discrete Event Dynamic Systems ; éd. Springer Verlag, 2023, vol. 33.
https://hal.science/hal-03952467v1

[2] I. Haur, J. Béchennec, O. H. Roux. Formal verification process of the compliance of a multicore AUTOSAR OS. In Software Quality Journal ; éd. Springer Verlag, 2023, vol. 31, num. 2.
https://hal.science/hal-04304216v1

[3] I. Haur, J. Béchennec, O. Roux. Model-Checking of Concurrent Real-Time Software Using High-Level Colored Time Petri Nets with Stopwatches. In Cybernetics and Systems ; éd. Taylor & Francis, 2023.
https://hal.science/hal-04685315v1

[4] J. Béchennec, D. Lime, O. Roux. Logical time control of concurrent DES. In Discrete Event Dynamic Systems ; éd. Springer Verlag, 2021.
https://hal.science/hal-03103458v1

[5] J. Béchennec, M. Brun, S. Faucou, L. Givel, O. Roux. Testing real-time systems with runtime enforcement. In IEEE Design & Test ; éd. IEEE, 2018.
https://hal.science/hal-01713193v1

[6] K. Tigori, J. Béchennec, S. Faucou, O. Roux. Formal Model-Based Synthesis of Application-Specific Static RTOS. In ACM Transactions on Embedded Computing Systems (TECS) ; éd. ACM, 2017, vol. 16, num. 4.
https://hal.science/hal-01713063v1

[7] S. Cotard, A. Queudet, J. Béchennec, S. Faucou, Y. Trinquet. STM-HRT: A Robust and Wait-Free STM for Hard Real-Time Multicore Embedded Systems. In ACM Transactions on Embedded Computing Systems (TECS) ; éd. ACM, 2015, vol. 14, num. 4.
https://hal.science/hal-01713171v1

[8] R. Kassem, M. Briday, J. Béchennec, G. Savaton, Y. Trinquet. Harmless, a Hardware Architecture Description Language Dedicated to Real-Time Embedded System Simulation. In Journal of Systems Architecture ; éd. Elsevier, 2012, vol. 58, num. 8.
https://hal.science/hal-00768517v1

[9] M. Briday, J. Béchennec, Y. Trinquet. Retis: a real-time simulation platform. In Journal Européen des Systèmes Automatisés (JESA) ; éd. Lavoisier, 2006, vol. 40, num. 8.
https://hal.science/hal-00537625v1

Conférences internationales avec comité de lecture et actes (COMM_INT)

[10] H. Reymond, J. Béchennec, M. Briday, S. Faucou, I. Puaut, E. Rohou. SCHEMATIC: Compile-time checkpoint placement and memory allocation for intermittent systems. In IEEE/ACM International Symposium on Code Generation and Optimization (CGO'24), mars 2024, Edinburgh, Royaume-Uni.
https://hal.science/hal-04345348v2

[11] H. Reymond, J. Béchennec, M. Briday, S. Faucou, I. Puaut, E. Rohou. EarlyBird: Energy belongs to those who wake up early. In RTCSA 2024 - 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, août 2024, Sokcho, Corée du Sud.
https://hal.science/hal-04663862v1

[12] S. Pillement, M. Mendez Real, J. Pottier, T. Nieddu, B. Le Gal, S. Faucou, J. Béchennec, M. Briday, S. Girbal, J. Le Rhun, O. Gilles, D. Gracia Pérez, A. Sintzoff, J. Coulon. Securing a RISC-V architecture: A dynamic approach. In 2023 Design, Automation and Test in Europe Conference (DATE 2023), avril 2023, Antwerp, Belgique.
https://hal.science/hal-03906564v1

[13] I. Haur, J. Béchennec, O. Roux. High-level Colored Time Petri Nets for true concurrency modeling in real-time software. In 2022 8th International Conference on Control, Decision and Information Technologies (CoDIT), mai 2022, Istanbul, Turquie.
https://hal.science/hal-03872207v1

[14] I. Haur, J. Béchennec, O. Roux. Formal schedulability analysis based on multi-core RTOS model. In RTNS '2021. The 29th International Conference on Real-Time Networks and Systems, avril 2021, Nantes, France.
https://hal.science/hal-03454818v1

[15] V. Lostanlen, A. Bernabeu, J. Béchennec, M. Briday, S. Faucou, M. Lagrange. Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds. In Proceedings of the International Workshop on the Internet of Sounds (IWIS), septembre 2021, Trento, Italie.
https://hal.science/hal-03324622v1

[16] K. Boukir, J. Béchennec, A. Déplanche. Requirement specification and model-checking of a real-time scheduler implementation. In 28th International Conference on Real-Time and Network Systems (RTNS 2020), juin 2020, Paris, France.
https://hal.science/hal-02941350v1

[17] J. Lagha, J. Béchennec, S. Faucou, O. Roux. Toward an Exact Simulation Interval for Multiprocessor Real-Time Systems Validation. In VALID 2020, The Twelfth International Conference on Advances in System Testing and Validation Lifecycle, octobre 2020, Lisbon, Portugal.
https://cnrs.hal.science/hal-03006791v1

[18] J. Béchennec, D. Lime, O. Roux. Control of DES with Urgency, Avoidability and Ineluctability. In 19th International Conference on Application of Concurrency to System Design (ACSD 2019), juin 2019, Aachen, Allemagne.
https://hal.science/hal-02415301v1

[19] J. Béchennec, D. Lime, O. Roux. Contrôle des SED avec urgence,évitabilité et inéluctabilité. In MSR 2019 - 12ème Colloque sur la Modélisation des Systèmes Réactifs, Nov 2019, Angers, France, novembre 2019, Angers, France.
https://hal.science/hal-02432148v2

[20] D. Solet, J. Béchennec, M. Briday, S. Faucou, S. Pillement. HW-based Architecture for Runtime Verification of Embedded Software on SOPC systems. In 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), août 2018, Edinburgh, Royaume-Uni.
https://hal.science/hal-01804096v1

[21] D. Solet, M. Briday, J. Béchennec, S. Faucou, S. Pillement. Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection. In 14th European Dependable Computing Conference (EDCC), septembre 2018, Iasi, Roumanie.
https://hal.science/hal-01874233v1

[22] K. Boukir, J. Béchennec, A. Déplanche. Formal approach for a verified implementation of Global EDF in Trampoline. In 26th International Conference on Real-Time Networks and Systems, octobre 2018, Chasseneuil-du-Poitou, France.
https://hal.science/hal-02004671v1

[23] K. Boukir, J. Béchennec, A. Déplanche. Reducing the gap between theory and practice: towards a proven implementation of Global-EDF in Trampoline. In JRWRTC 2017 - 11th Junior Researcher Workshop on Real-Time Computing, octobre 2017, Grenoble, France.
https://hal.science/hal-01708851v1

[24] A. Mangean, J. Béchennec, M. Briday, S. Faucou. WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction. In Verification and Evaluation of Computer and Communication Systems. VECoS 2017, août 2017, Montréal, Canada.In Kamel Barkaoui (éds.), . Springer, 2017.
https://hal.science/hal-01713094v1

[25] D. Solet, J. Béchennec, M. Briday, S. Faucou, S. Pillement. Hardware runtime verification of embedded software in SoPC. In 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), mai 2016, Cracovie, Pologne.
https://hal.science/hal-01307973v1

[26] L. Givel, J. Béchennec, M. Brun, S. Faucou, O. Roux. Testing real-time embedded software using runtime enforcement. In 11th IEEE International Symposium on Industrial Embedded Systems, IEEE SIES 2016, mai 2016, Krakow, Pologne.
https://hal.science/hal-01399909v1

[27] A. Mangean, J. Béchennec, M. Briday, S. Faucou. BEST: a Binary Executable Slicing Tool. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016), juillet 2016, Toulouse, France.In Martin Schoeberl (éds.), . Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik, 2016.
https://hal.science/hal-01713140v1

[28] K. Tigori, J. Béchennec, O. Roux. Formal Synthesis of Optimal RTOS. In 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems., août 2015, New York, états-Unis.
https://hal.science/hal-01413492v1

[29] K. Tigori, J. Béchennec, S. Faucou, O. Roux. Using formal methods for the development of safe application-specific RTOS for automotive systems. In CARS 2015 - Critical Automotive applications: Robustness & Safety, septembre 2015, Paris, France.In Matthieu Roy (éds.), . , 2015.
https://hal.science/hal-01193023v1

[30] K. Gautier Tigori, J. Béchennec, O. Roux. Approche formelle pour la spécialisation de systèmes d'exploitation temps réel. In Modélisation des Systèmes Réactifs (MSR 2015), novembre 2015, Nancy, France.In Stephan Merz and Jean-François Pétin (éds.), . , 2015.
https://inria.hal.science/hal-01224465v1

[31] J. Tanguy, J. Béchennec, M. Briday, O. Roux. Reactive Embedded Device Driver Synthesis using Logical Timed Models. In 4th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH 2014), août 2014, Vienne, Autriche.
https://hal.science/hal-01142411v1

[32] J. Tanguy, J. Béchennec, M. Briday, S. Dubé, O. Roux. Device driver synthesis for embedded systems. In 18th IEEE International Conference on Emerging Technologies & Factory Automation, septembre 2013, Cagliari, Italie.
https://hal.science/hal-00942323v1

[33] A. Bullich, M. Briday, J. Béchennec, Y. Trinquet. A compiled Cycle Accurate Simulation for Hardware Architecture. In 5th International Conference on Advances in System Simulation - SIMUL 2013, octobre 2013, VENICE, Italie.
https://hal.science/hal-00943401v1

[34] S. Faucou, S. Cotard, J. Béchennec, A. Queudet, Y. Trinquet. A Data Flow Monitoring Service Based on Runtime Verification for AUTOSAR. In 2012 IEEE 14th Int'l Conf. on High Performance Computing and Communication (HPCC) & 2012 IEEE 9th Int'l Conf. on Embedded Software and Systems (ICESS), juin 2012, Liverpool, Royaume-Uni.
https://hal.science/hal-01713202v1

[35] G. Savaton, J. Béchennec, M. Briday, R. Kassem. An Architecture Description Language for Embedded Hardware Platforms. In Workshop on OCL and Textual Modelling, TOOLS 2011, 2011, Zürich, Anguilla.
https://hal.science/hal-01179758v1

[36] J. Béchennec, M. Briday, V. Alibert. Extending HARMLESS Architecture Description Language for Embedded Real-Time Systems Validation. In IEEE International Symposium on Industrial Embedded Systems, juin 2011, Västerås, Suède.
https://hal.science/hal-00941186v1

[37] R. Kassem, M. Briday, J. Béchennec, Y. Trinquet, G. Savaton. Instruction set simulator generation using Harmless, a new hardware architecture description language. In 2nd Int. Conf. on Simulation Tools and Techniques for Communications, Networks ans Systems (Simutools 2009), mars 2009, Roma, Italie.
https://inria.hal.science/inria-00538502v1

[38] R. Kassem, M. Briday, J. Béchennec, Y. Trinquet, G. Savaton. Cycle accurate simulator generator using Harmless. In Int. Middle Eastern Multiconference on Simulation and Modelling (MESM'09), septembre 2009, Beirut, Liban.
https://inria.hal.science/inria-00538508v1

[39] R. Kassem, M. Briday, J. Béchennec, Y. Trinquet, G. Savaton. Simulator Generation Using an Automaton Based Pipeline Model for Timing Analysis.. In International Multiconference on Computer Science and Information Technology (IMCSIT), International Workshop on Real Time Software (RTS'08)., octobre 2008, Wisla, Pologne.In IEEE (éds.), Proceedings of the International Multiconference on Computer Science and Information Technology.. , 2008.
https://hal.science/hal-00486839v1

[40] J. Béchennec, M. Briday, S. Faucou, Y. Trinquet. Trampoline - an open source implementation of the osek/vdx rtos specification. In 11th Int. Conf. on Emerging Technologies and Factory Automation (ETFA'06), septembre 2006, Prague, République tchèque.
https://inria.hal.science/inria-00538492v1

Conférences nationales avec comité de lecture et actes (COMM_NAT)

[41] A. Bernabeu, J. Béchennec, M. Briday, S. Faucou, O. Roux. MORTEM: a new runtime for intermittent computing. In Conférence francophone d'informatique en Parallélisme, Architecture et Système (COMPAS), juillet 2023, Annecy, France.
https://hal.science/hal-04354069v1

[42] A. Bernabeu, J. Béchennec, M. Briday, S. Faucou, O. Roux. Synthèse de traces temporisées à coût optimal pour l'ordonnancement de systèmes embarqués intermittents. In Modélisation des Systèmes Réactifs (MSR'21), novembre 2021, Paris, France.
https://hal.science/hal-03449539v1

Autres publications (AUTRES)

[43] H. Reymond, I. Puaut, E. Rohou, S. Faucou, J. Béchennec, M. Briday. Memory Allocation in Intermittent Computing. In COMPAS'2022, juillet 2022, Amiens, France.
https://hal.science/hal-04385204v1

[44] J. Béchennec, A. Bernabeu, M. Briday, S. Faucou. Support d'exécution pour le calcul intermittent. In COMPAS 2021, juillet 2021, Lyon, France.
https://hal.science/hal-03446983v1

[45] D. Solet, S. Pillement, M. Briday, J. Béchennec, S. Faucou. Implémentation matérielle d’un dispositif de vérification en ligne sur un SoPC. In Colloque National GDR SoC-SiP, juin 2016, Nantes, France.
https://hal.science/hal-01324796v1